The present invention relates to control of a cache memory.
With a speedup of a CPU, it is an important factor in terms of improving a capacity of a whole system to efficiently control the cache memory.
In a system having a snoop tag representing (specifying a location of) a copy of the cache memory (which will hereinafter simple be referred to as a cache) built in the CPU, if the WAY to the cache is filled with the data, a READ request due to a cache miss is issued to the system.
At this time, if there is no means by which the CPU notifies the system of REPLACE information showing which WAY is swept out, the system side has no alternative but to determine at its own discretion which WAY to the snoop tag is swept out.
In this case, if the WAY swept out by the CPU is different from the WAY swept out by the system side, a cache miss rate rises resultantly. Herein, a premise is a protocol that independently issues the REPLACE information as another REPLACE request to the system from the CPU. This REPLACE request contains, as its content, not the WAY information but only the address information, whereby the system side can recognize from a result of searching through the snoop tag which WAY should be swept out.
Accordingly, the effect is reduced down to a half unless the REPLACE request is processed earlier than a READ request paired with the REPLACE request, and hence it is required that the REPLACE request be surely processed ahead of the READ request.
Further, if the request is pipeline-processed within the system, a general method is that the read and the write of the snoop tag are processed at different timings from requirements of latency, however, in this case it must be assured that there are none of different accesses to the same index between the read and the write. Namely, a so-called index lock must be done.
Moreover, technologies disclosed in the following Patent documents 1 and 2 are given as prior arts related to the invention of the present application.
[Patent document 1] Japanese Patent Application Laid-Open Publication No. 04-71049
[Patent document 2] Japanese Patent Application Laid-Open Publication No. 11-102320